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Using SPI Master Mode in FreeRTOS

Using SPI Master Mode in FreeRTOS

Owned by Natalia Sofronova
Last updated: May 22, 2024
4 min read

This application note explains how to use the STM32H7 SPI Master mode in the FreeRTOS demo application.

1. Understanding SPI Master Mode Interfaces

1.1. FreeRTOS SPI Master Mode Implementation

The FreeRTOS BSP provides a device driver for the SPI Master mode operation. The driver is configured (enabled / disabled) at the BSP build time, using the HAL_SPI_MODULE_ENABLED configuration option, defined in the stm32h7xx_hal_conf.h file.

1.2. FreeRTOS SPI Master Mode C-Binding API

The SPI Master Mode driver implements the following C-binding API:

Function

Description

Comments

HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef * hspi)

 

Initialise the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle

hspi is a pointer to a structure that contains the configuration information for SPI; returns one of {HAL_OK, HAL_ERROR, HAL_BUSY, HAL_TIMEOUT}

HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef * hspi)

 

De-initialise the SPI peripheral

hspi is a pointer to a structure that contains the configuration information for SPI; returns one of {HAL_OK, HAL_ERROR, HAL_BUSY, HAL_TIMEOUT}

HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef * hspi, uint8_t * pData, uint16_t Size, uint32_t Timeout)

 

Receive an amount of data in blocking mode

hspi is a pointer to a structure that contains the configuration information for SPI; pData is a pointer to a data buffer; Size is an amount of data to be received; Timeout is a timeout duration; returns one of {HAL_OK, HAL_ERROR, HAL_BUSY, HAL_TIMEOUT}

HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef * hspi, uint8_t * pData, uint16_t Size, uint32_t Timeout)

 

Transmit an amount of data in blocking mode

hspi is a pointer to a structure that contains the configuration information for SPI; pData is a pointer to a data buffer; Size is an amount of data to be received; Timeout is a timeout duration; returns one of {HAL_OK, HAL_ERROR, HAL_BUSY, HAL_TIMEOUT}

The SPI_HandleTypeDef data structure used in this API has the following definition:

typedef struct __SPI_HandleTypeDef { SPI_TypeDef * Instance; /* SPI registers base address */ SPI_InitTypeDef Init; /* SPI communication parameters */ uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */ uint16_t TxXferSize; /* SPI Tx Transfer size */ __IO uint16_t TxXferCount; /* SPI Tx Transfer Counter */ uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */ uint16_t RxXferSize; /* SPI Rx Transfer size */ __IO uint16_t RxXferCount; /* SPI Rx Transfer Counter */ uint32_t CRCSize; /* SPI CRC size used for the transfer */ void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Rx ISR */ void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Tx ISR */ DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA Handle parameters */ DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA Handle parameters */ HAL_LockTypeDef Lock; /* Locking object */ __IO HAL_SPI_StateTypeDef State; /* SPI communication state */ __IO uint32_t ErrorCode; /* SPI Error code */ } SPI_HandleTypeDef;

The SPI_InitTypeDef data structure used in SPI_HandleTypeDef has the following definition:

typedef struct { uint32_t Mode; /* Specifies the SPI operating mode. */ uint32_t Direction; /* Specifies the SPI bidirectional mode state. */ uint32_t DataSize; /* Specifies the SPI data size. */ uint32_t CLKPolarity; /* Specifies the serial clock steady state. */ uint32_t CLKPhase; /* Specifies the clock active edge for the bit capture. */ uint32_t NSS; /* Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. */ uint32_t BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which used to configure the transmit and receive SCK clock. */ uint32_t FirstBit; /* Specifies whether data transfers start from MSB or LSB bit. */ uint32_t TIMode; /* Specifies if the TI mode is enabled or not. */ uint32_t CRCCalculation; /* Specifies if the CRC calculation is enabled or not. */ uint32_t CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */ uint32_t CRCLength; /* Specifies the CRC Length used for the CRC calculation. */ uint32_t NSSPMode; /* Specifies whether the NSSP signal is enabled or not. */ uint32_t NSSPolarity; /* Specifies which level of SS input/ output external signal (present on SS pin) is considered as active one. */ uint32_t FifoThreshold; /* Specifies the FIFO threshold level.*/ uint32_t TxCRCInitializationPattern; /* Specifies the transmitter CRC initialization Pattern used for the CRC calculation.*/ uint32_t RxCRCInitializationPattern; /* Specifies the receiver CRC initialization Pattern used for the CRC calculation. */ uint32_t MasterSSIdleness; /* Specifies an extra delay, expressed in number of SPI clock cycle periods, inserted additionally between active edge of SS and first data transaction start in master mode. */ uint32_t MasterInterDataIdleness; /* Specifies minimum time delay (expressed in SPI clock cycles periods) inserted between two consecutive data frames in master mode. */ uint32_t MasterReceiverAutoSusp; /* Control continuous SPI transfer in master receiver mode and automatic management in order to avoid overrun condition. */ uint32_t MasterKeepIOState; /* Control of Alternate function GPIOs state. */ uint32_t IOSwap; /* Invert MISO/MOSI alternate functions. */ } SPI_InitTypeDef;

2. SPI Master Mode CLI Command

The FreeRTOS application implements the following SPI Master mode related CLI command:

Command

Description

Comments

spi_flash_test <bus>

Read the SPI flash device ID

bus is the SPI bus number SPI Flash resides on

3. Validating SPI Master Operation

Use the following step-wise procedure to validate the SPI Master mode operation:

  1. Connect a m25p32 SPI Flash device (or a similar Flash device) to the SPI1 pins on the carrier board:

    • On the STM32H7-BSB Rev 1A board: P2.15 (MISO/PG9), P2.16 (MOSI/PD7), P2.13 (nSS/PG10), P2.12 (SCK/PG11);

    • On the STM32H7-BSB Rev 2A board: P2.3 (MISO/PG9), P2.4 (MOSI/PD7), P2.5 (nSS/PG10), P4.3 (SCK/PA5).

  2. From the FreeRTOS CLI, run the SPI test:

    CLI> spi_flash_test 1 Manufacturer ID:0x20 Device ID:0x2016 CFD Length:0x10

  3. Compare the output of the spi_flash_test command with the result of the 0x9F command taken from the datasheet for the m25p32 SPI Flash device and listed in the table below:

Manufacturer Identification

Device Identification

CFD Length

Manufacturer Identification

Device Identification

CFD Length

0x20

0x2016

0x10