This document describes the hardware architecture of the Emcraft Systems nRF9151 System-on-Module (referred to as “nRF9151 SOM” hereafter).
The nRF9151 SOM is intended to provide a low-cost flexible platform for embedded solutions that require rich connectivity and flexibility of the nRF9151 System-in-Package (SiP). The nRF9151 SOM is based on the NORDIC® Semiconductor nRF9151 (SiP) supporting LTE-M, NB-IoT, GNSS and NR+. The Zephyr kernel and applications execute on the. The integrated peripheral controllers of the nRF9151 are used to implement various communication, connectivity and human-machine interfaces.
Using a miniature mezzanine form factor, the nRF9151 SOM is specifically designed to provide a battery-operated platform for cellular IoT on various boards targeting industrial automation, system and power management, wired and wireless networking / sensors and other embedded applications. The nRF9151 SOM is architected as a low-cost solution with flexibility in customizing its functionality for the needs of particular products and customers.
This section defines the hardware platform of the nRF9151 SOM.
The following are the key hardware features of the nRF9151 SOM:
Compact mezzanine module (30.5mm x 55mm);
External interfaces using two 50-pin 0.4mm-pitch connectors;
Two mounting holes reducing the risk of connector-to-PCB intermittence;
Compliant with the Restriction of Hazardous Substances (RoHS) directive;
NORDIC® Semiconductor nRF9151 System-in-Package (SiP) with ARM® Cortex®-M33 64 MHz processor core;
SWD interface to the nRF9151 on the interface connectors;
Powered from a +5V power supply and/or a 1cell 3.7V rechargeable LiIon/Li-Po battery;
Low-power operational modes with fast wake-up;
16MBytes SPI Flash memory;
On-module clocks;
nPM1300 PMIC for battery charging and fuel gauging;
A 3.0V power output for external devices on the interface connectors;
2 software configurable power regulator outputs (1.0V-3.0V) up to 200mA in total on the interface connectors;
Output power for external devices: VSYS (from either VIN/VBUS or VBAT_C input) and VBUSOUT - available when VIN/VBUS is present
Serial console interface at the UART CMOS levels;
A Nano/4FF SIM card slot, supporting (e)SIM;
An optional MFFx M2M UICC SIM Card;
An I-PEX MHF1/u.Fl connector for a LTE antenna;
An I-PEX MHF1/u.Fl connector for a GNSS antenna;
An RF amplifier for GNSS;
A Real Time Clock;
Various serial digital (UART, SPI, I2C, I2S, PWM, PDM) and analog interfaces of the nRF9151 available on the interface connectors.
The following figure is a functional block diagram of the on the interface connectors:
The architecture of the nRF9151 SOM is built around the NORDIC Semiconductor nRF9151 SPI that combines the ARM® Cortex®-M33 64 MHz processor core with a wide range of the integrated peripheral controllers.
The nRF9151 contains a 1MB Flash memory and 236kB low leakage RAM.
The nRF9151 device is implemented using the 12.1mm x 11.1mm 0.5mm-pitch Map LGA package.
The nRF9151 SOM provides a two-pin SWD interface (the SWDIO and SWDCLK signals) on the interface connectors. This interface is routed to the corresponding signals of the nRF9151 device.
The nRF9151 is run from two power sources provided through multiple pins on the interface connectors:
A USB Type C compliant +5V source (VIN/VBUS);
A 1cell rechargeable Li-Po battery (VBAT_C/VBAT).
The power architecture of the nRF9151 SOM is based on the NORDIC Semiconductor nPM1300 PMIC, which has several power and system management features, including (refer to NRF9151 SOM Functional Block Diagram for a graphic view of circuit connections):
System regulator (SYSREG) of the PMIC supplies main power rail VSYS from:
VBUS (VIN from an AC wall adapter or a USB port- if/when they are present);
Battery (VBAT_C): when a battery is connected but VIN (VBUS) isn’t present;
The VSYS voltage is 4V-5.5V when it is supplied from the VIN (VBUS) (+5V power is present) and 3.2V-4.4V when it is supplied from the Battery/VBAT_C (+5V power isn’t present)
Two 200mA BUCK regulators:
§ BUCK2 (VOUT2) @ 3.0V is used on the SOM and broken out to the SOM interface connectors;
§ BUCK1 is disabled by default, may be enabled and configured by software to a 1.0V-3.0V output voltage. It is available on SOM interface connectors;
Two LDO/Load Switches :
§ LDO1/LSW1 gets power from the BUCK1 output. LDO1/LSW1 is disabled by default, may be enabled and configured by software to a 1.0V-3.0V output voltage. It is available on the SOM interface connectors;
§ LDO2/LSW2 isn’t used in the nRF9151 SOM
SYSREG provide the following features:
Operating voltage up to 5.5 V
Overvoltage protection to 22 V
Undervoltage detection
USB port detection and a current limiter to comply with the USB specification
Provides VBUSOUT voltage
In the nRF9151 SOM, the nPM1300 supplies VBUSOUT voltage on the SOM interface connectors when VIN (VBUS) voltage is present. VBUSOUT provides overvoltage and undervoltage protection for safe connection to external devices.
The nPM1300 supports the USB PD Configuration Channel functionality.
The PMIC VIN (VBUS) input current limiter manages VIN (VBUS) current limitation and charger detection for USB Type-C compatible chargers. The VIN (VBUS) current limit value is configurable by software.
The PMIC battery charger is suitable for general purpose applications with lithium-ion (Li-ion), lithium-polymer (Li-poly), and lithium iron phosphate (LiFePO4) batteries.
nPM1300 supports charging up to 800 mA and delivers up to 500 mA of adjustable regulated voltage.
Resistor R110 0 Ohm 0805/1210 is connected between the battery connector pin and the nPM1300 VBAT input. Customers can replace it with a current sense resistor or temporarily remove this resistor for battery current measurements. An amperemeter must be connected between TP20 and TP22 in the latter case.
The nRF9151 SOM supports the following power modes:
Full-power mode. This is the normal mode of operation. The main clock is running and the CPU core is running Zephyr. All memory controllers are enabled. Software is configured to enable only those nRF9151 sub-systems that are used by installed device drivers; the clocks to all other sub-systems are gated off so those modules do not consume power.
Low-power mode. The low power mode is default after power-on reset. The nRF9151 SOM remains in the low-power mode until woken up by a configured trigger (such as, for instance, activation of a configured GPIO). On occurrence of a wake-up trigger, the nRF9151 SOM returns to the full-power mode.
The nRF9151 SOM implements a reset architecture that ensures that the nRF9151 microprocessor is reset as appropriate on various hardware and software events.
The following types of reset are implemented by the nRF9151 SOM:
Power-on reset. This type of reset occurs when the power is initially applied to the SOM- NRF9151. As the supply voltage rises, the nRF9151 Power Management Unit (PMU) voltage supervisor holds the nRF9151 in reset until all the nRF9151 power supply voltage (VSYS) have risen above the VPOR voltage threshold (Maximum 3.0V).
Brown-out reset. In case the nRF9151 VSYS supply falls below its brown-out voltage threshold (VBOR ) the nRF9151 PMU generates a reset of the nRF9151. The typical value of VBOR= 2.8V.
The aforementioned resets can be initiated by starting power cycle on the SOM using the nPM1300 PMIC functionality as follows:
By connecting the SHPHLD nPM1300 pin/circuit to the ground for longer than 10s time. The SHPHLD SOM circuit is available on Test Point TP14.
Appropriately configuring the PMIC watchdog timer. A power cycle is started when the PMIC WDT expires
Hardware reset. This type of reset is activated by connecting pin nRESET of the nRF9151 to the Ground. This pin is connected via a RC-net to circuit SWD_nRST of the nRF9151 SOM and it is available on Test Point TP7 and the SOM connector. This circuit/reset is used by SWD debuggers/programmers.
Software reset. This type of reset is activated by software running on the nRF9151 SOM through performing the nRF9151 software reset sequence.
WDT reset. This type of reset is activated when the integrated nRF9151 WDT expires.
External reset. To activate this type of reset, a baseboard drives low the SWD_nRST signal on the nRF9151 SOM interface connectors.
The nRF9151 SOM uses internal oscillators in nRF9151:
64MHz oscillators (HFINT) and high accuracy oscillator (HFXO);
32.768 kHz RC oscillator (LFRC) and 32.768 kHz high accuracy oscillator (LFXO).
The RTC uses 32.768 kHz oscillator with an external 32.768 kHz crystal.
The nRF9151 SOM provides 16MBytes of SPI Flash memory using the Winbond W25Q128JVPIQ device. Compatible 4-8MBytes devices can also be used.
Ship and Hibernate modes isolate the battery from the system and minimize the quiescent current.
Hibernate mode is identical to Ship mode with the exception that, in Hibernate mode, the timer is running and functions as an additional wake-up source (refer to Section: “nPM1300 Watchdog/Timers”).
The device enters Ship mode by software. When VIN (VBUS) is not present, the device enters Ship mode immediately.
The following are alternative ways to exit Ship modes:
Pulling pin SHPHLD low for 16ms-3s, configured by software, the default value is 96ms. A push button to GND is required.
Applying a voltage on VIN (VBUS) > 3.9V.
The device enters Hibernate mode by software. In Hibernate mode, the quiescent current is higher compared to Ship mode because the low-power timer is running.
The following are alternative ways to exit Hibernate modes:
Pulling pin SHPHLD low for 16ms-3s, configured by software, the default value is 96ms. A push button to GND is required.
Applying a voltage on VIN (VBUS) > 3.9V;
Exiting automatically through the Wake-up timer.
The nRF9151 SiP in the NRF9151 SOM contains a Low-Power Wide-Area (LPWA) network processor with dedicated flash/RAM, which controls the radio and baseband hardware components. LTE capabilities are provided by installing Nordic Semiconductor firmware, which complies with 3GPP LTE release 14 Cat-M1 and Cat-NB1/NB2 standards.
nRF9151 SOM supports the following bands: B1, B2, B3, B4, B5, B8, B12, B13, B17, B19, B20, B25, B26, B28, B65, B66, B85;
Cat-M1 Maximum transmission bandwidth: 1.4MHz;
Cat-NB1 and Cat-NB2 Maximum transmission bandwidth: 200kHz;
Cat-M1 typical receiver sensitivity at low and mid bands -108dBm and -107dBm respectively;
Cat-NB1 and Cat-NB2 typical receiver sensitivity at low and mid bands -114dBm and -113dBm respectively;
Class 3 and Class 5 maximum output powers 23dBm and 20dBm respectively.
The nRF9151 SOM provides signal LTE_COEX2 that is the output from the LTE modem to the external device. When active high, this indicates that the LTE modem transceiver is turned on. COEX2 can also be treated as an active low grant from the LTE modem to the external device, indicating permission to transmit and receive. The LTE_COEX2 signal is available on the SOM connectors.
Note: Using the COEX2 pin (the LTE_COEX2 signal) requires an external pull-down resistor in the 100 kΩ range.
The nRF9151 SOM supports a SIM card. It has a pluggable SIM card socket (J3 on the bottom) that is compatible with a nano-sized SIM (4FF). The The nRF9151 SOM has also an unpopulated eSIM footprint (U21) that can be populated with a compatible MFF2 M2M eSIM IC.
In the nRF9151 SOM the SiP LTE modem is supplied from the VSYS power rail with voltage from 3.2V to 5.5V. Refer to VSYS voltage for detail.
The nRF9151 SOM contains I-PEX MHF1/u.Fl connector J1 for an LTE antenna. The Quectel YF0022DA or a similar antenna is recommended for using with nRF9151 SOM.
The nRF9151 SOM has a dedicated Global Navigation Satellite System (GNSS) port to support global navigation. GNSS functionality requires support in the onboard network protocol firmware.
The GNSS signal is received from an external GNSS antenna via MHF1/u.FL connector J2 and Low-Noise Amplifier (LNA) U1. The LNA is enabled by a GNSS-enable signal from the nRF9151 using the COEX0 pin.
To optimize GNSS reception, do the following:
GNSS signals do not usually penetrate ceilings or other structures that well. For best GNSS performance, the nRF9151 SOM should be placed outside on a flat surface in an open space far from sources of interference and other structures that can block the satellite signals.
The Antenova SRFG017 or a similar antenna is recommended for using with the NRF9151 SOM.
The nRF9151 SiP in the NRF9151 SOM contains a Low-Power Wide-Area (LPWA) network processor with dedicated flash/RAM, which controls the radio and baseband hardware components. DECT NR+ (NR+) capabilities are provided by installing Nordic Semiconductor firmware, that implements the physical layer (PHY) level operation of the NR+ radio protocol stack according to ETSI specifications (TS 103 636-2 and TS 103 636-3).
NR+ operates on the global and license-exempt 1.9 GHz band, which significantly cuts deployment costs by eliminating the need for frequency planning or heavy certification.
Note: While running DECT NR+ firmware, the nRF9151 SOM does not support LTE modem.
License-exempt global band;
Built-in coexistence of multiple networks in the same location;
Flexible, low-latency system and network architectures;
High reliability, using hybrid ARQ;
Possibility of hiding the network, using AES-128 encryption and integrity protection;
Data rate up to 3.4 Mbps, depending on modulation;
The nRF9151 SOM supports NR+ bands 1, 2, and 9;
Transmission Bandwidth: 1.728MHz;
RX: Sensitivity, modulation MCS1: -103dBm;
TX: Maximum output power: 19dBm.
NR+ uses a dedicated two-pin coexistence interface to avoid RF interference to a companion radio device such as an external positioning device or a Bluetooth Low Energy device.
The user can configure COEX0 and COEX2 pin functions through the NR+ AT commands. Pin COEX0 is used on the SOM to control the GNSS RF LNA. Pin COEX2 (the LTE_COEX2 signal) is available on the SOM connectors.
Note: Using the COEX2 pin (the LTE_COEX2 signal) requires an external pull-down resistor in the 100 kΩ range.
DECT NR+ in the NRF9151 SOM uses the same antenna as the LTE modem, refer to LTE Antenna for detail.
The nRF9151 SOM provides UART serial interfaces at CMOS levels (no RS-232 buffers) using the integrated UARTE controller of the nRF9151 SOM MCU. on the interface connector.
The UART controllers feature an internal divider that allows these serial interfaces to operate at standard baud rates up to 1Mbit/s. The default firmware setting is 115200 bps.
The nRF9151 provides a hardware watchdog function using the integrated watchdog dedicated to MCU.
The watchdog is disabled by default after the reset. Software should enable or leave them disabled, as appropriate.
If software enables a WDOG and then fails to refresh it within the predefined period of time, the watchdog resets the corresponding module of the nRF9151.
The watchdog timeout period is defined by software.
The Watchdog is one of the function of the nPM1300 timer which are as follows:
Boot monitor;
Watchdog timer;
Wake-up timer;
General purpose timer.
Only one of these functions can be selected at one time.
After power-up/power-on reset, when all the input power supplies of nPM1300 are disabled, the aforementioned timers/monitor are disabled,
nPM1300 Boot monitor: when enabled, it allows an automatic power cycle if the host does not set an appropriate bit in a nPM1300 register (via the I2C bus) during 10s.
Watchdog timer : Watchdog timer expiration can be configured by host software to generate an NRESETOUT through a GPIO or a power cycle (the default function).
Wake-up timer: The wake-up timer wakes the system from Hibernate mode. Refer to Section: “PMIC Hibernate Mode”.
The nRF9151 SOM provides a Real-Time Clock (RTC) feature using the NXP PCF85263ATL device. The RTC provides a time-of-day clock/calendar with programmable alarm and periodic interrupts. The alarm/interrupt features are not supported when the PMIC is in Ship or Hibernate mode.
The VBAT power (a battery) is used as a backup power for the RTC in when the PMIC is in Ship and Hibernate mode or during PMIC power cycles.
In the nRF9151 SOM the RTC is clocked by an external crystal via the internal oscillator. This oscillator is in the same backup power domain as the RTC.
The nRF9151 SOM uses the RTC device as a source for time-stamps of various system events.
The external interfaces of the nRF9151 SOM are routed through two 50-pin Hirose DF40 series 0.4mm-pitch board-to-board connectors.
Refer to SOM-NRF9151 Pin-Out for detail on SOM connectors pin-out.
The nRF9151 SOM provides the following signal and power rail on Test Points:
TP # | Signal/Rail Name | Function | Notes | |
|---|---|---|---|---|
| 1 | TP1 | UART_RX | nRF9151 UART RxD | It is the output (via R3) of buffer U5 (74LVC1G34GW,125). The input of this buffer is connected to BSB_TXD/TP8. |
| 2 | TP2 | UART_TX | nRF9151 UART TxD | Via R4 |
| 3 | TP3 | SDA | I2C Serial Data | Connected to nPM1300 pin 13/SDA |
| 4 | TP4 | SCL | I2C Serial clock | Connected to nPM1300 pin 14/SCL |
| 5 | TP5 | SWDCLK | Serial wire debug clock input for debug and programming | |
| 6 | TP6 | SWDIO | Serial wire debug I/O for debug and programming | |
| 7 | TP7 | SWD_nRST | nRF9151 reset input | Connected to nRF9151 pin 6/nRESET via an RC-net (R59/C10) |
| 8 | TP8 | BSB_TXD | Input to nRF9151 UART console from the SOM connector | Connected to the input of buffer U5 |
| 9 | TP10 | SPI-CLK | Serial Clock for the SPI Flash memory | |
| 10 | TP11 | SPI-MOSI | Data output to the SPI Flash memory | |
| 11 | TP12 | SPI-MISO | Data input from the SPI Flash memory | |
| 12 | TP13 | SPI_nSS | Slave select to the SPI Flash memory | |
| 13 | TP14 | SHPHLD | A nPM1300 reset control, in addition to being used for exiting Ship and Hibernate mode | Connected to nPM1300 pin15/SHPHLD |
| 14 | TP20 | VBAT_C | Battery power input | Connected to R110 |
| 15 | TP21 | VSYS | The nPM1300 power output (3.2V-5.5V) | Refer to VSYS power |
| 16 | TP22 | VBAT | Battery power after the serial resistor R110, the nPM1300 input | Connected to nPM1300 pin 19/VBAT |
| 17 | TP23 | VBUS | nPM1300 +5V power input (from the USB VBUS or an external power supply)Connect | Connected to nPM1300 pin 21/VBUS |
| 18 | TP24, TP25, TP26, TP27 | GND | SOM ground | |
| 19 | TP28 | 3V0 | 3.0V power supply from the nPM1300 BUCK1 output |
The nRF9151 SOM is implemented as a miniature 30.5mm x 55mm x 2.6mm module. Note: the height is with a mated antenna cable.
The nRF9151 SOM PCB thickness is 1.6+/- 0.16mm. The maximum height of the SOM components on the both sides of the module is 2.6mm with a mated antenna cable. Without antenna cables, the maximum height of the SOM components on the both sides of the module is 1.45mm.
The nRF9151 SOM includes two mounting holes so that the module can be mechanically secured to a baseboard, reducing the risk of connector-to-PCB intermittence that might occur during NEBS vibration and earthquake testing (or during real events that those tests simulate).
The following figure shows the location of the mounting holes and the SOM connectors on the module:
On a baseboard, the nRF9151 SOM is installed into two 50-pin Hirose DF40 series 0.4mm-pitch board-to-board connectors. The exact part number of the connectors is Hirose DF40C-50DP-0.4V. Mechanical details of the connectors can be found in the corresponding datasheet.
The recommended mating connectors for a baseboard is the Hirose DF40HC(4.0)-50DS-0.4V(51) connector, which provides 4mm stacking height for the nRF9151 SOM. The maximum height of the SOM above a baseboard for 4mm stacking height is 9.52mm.
The following pictures provide the top and bottom views of the nRF9151 SOM:
The following table lists the recommended operating conditions for the Industrial Temp range variant of the nRF9151 SOM:
Symbol | Parameter | Range | |
TA | Ambient temperature | Industrial | -40ºC to +85 ºC |
TC | nRF9151 case operational temperature1 | -40ºC to +85 ºC | |
VIN | External power (USB_VBUS) supply | From 4.0V to 5.5V | |
VBAT_C | Battery voltage | From 3.2V to 4.35V | |
The optimal operating case temperature (Tc) of nRF9151 ranges from –30°C to 65°C, achieving the best RF performance including output power transmission and receiver sensitivity.
Revision | Date | Changes Summary |
1.0 | February 27, 2025 | Initial version |