This application note explains how to use the STM32H7 SPI Master mode in the FreeRTOS demo application.

1. Understanding SPI Master Mode Interfaces

1.1. FreeRTOS SPI Master Mode Implementation

The FreeRTOS BSP provides a device driver for the SPI Master mode operation. The driver is configured (enabled / disabled) at the BSP build time, using the HAL_SPI_MODULE_ENABLED configuration option, defined in the stm32h7xx_hal_conf.h file.

1.2. FreeRTOS SPI Master Mode C-Binding API

The SPI Master Mode driver implements the following C-binding API:

Function	Description	Comments
`HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef * hspi)`
	Initialise the SPI according to the specified parameters in the `SPI_InitTypeDef` and initialize the associated handle	`hspi` is a pointer to a structure that contains the configuration information for SPI; returns one of `{HAL_OK, HAL_ERROR, HAL_BUSY, HAL_TIMEOUT}`
`HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef * hspi)`
	De-initialise the SPI peripheral	`hspi` is a pointer to a structure that contains the configuration information for SPI; returns one of `{HAL_OK, HAL_ERROR, HAL_BUSY, HAL_TIMEOUT}`
`HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef * hspi, uint8_t * pData, uint16_t Size, uint32_t Timeout)`
	Receive an amount of data in blocking mode	`hspi` is a pointer to a structure that contains the configuration information for SPI; `pData` is a pointer to a data buffer; `Size` is an amount of data to be received; `Timeout` is a timeout duration; returns one of `{HAL_OK, HAL_ERROR, HAL_BUSY, HAL_TIMEOUT}`
`HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef * hspi, uint8_t * pData, uint16_t Size, uint32_t Timeout)`
	Transmit an amount of data in blocking mode	`hspi` is a pointer to a structure that contains the configuration information for SPI; `pData` is a pointer to a data buffer; `Size` is an amount of data to be received; `Timeout` is a timeout duration; returns one of `{HAL_OK, HAL_ERROR, HAL_BUSY, HAL_TIMEOUT}`

The SPI_HandleTypeDef data structure used in this API has the following definition:

Code Block

typedef struct __SPI_HandleTypeDef
{
    SPI_TypeDef  *             Instance;             /* SPI registers base 
                                                        address         */
    SPI_InitTypeDef            Init;                 /* SPI communication 
                                                        parameters       */
    uint8_t                    *pTxBuffPtr;          /* Pointer to SPI Tx 
                                                        transfer Buffer  */
    uint16_t                   TxXferSize;           /* SPI Tx Transfer size               
                                                      */
    __IO uint16_t              TxXferCount;          /* SPI Tx Transfer Counter            
                                                      */
    uint8_t                    *pRxBuffPtr;          /* Pointer to SPI Rx 
                                                        transfer Buffer  */
    uint16_t                   RxXferSize;           /* SPI Rx Transfer size   */
    __IO uint16_t              RxXferCount;          /* SPI Rx Transfer Counter 
                                                      */
    uint32_t                   CRCSize;              /* SPI CRC size used for 
                                                        the transfer */
    void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer 
                                                        on Rx ISR         */
    void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on 
                                                        Tx ISR         */
    DMA_HandleTypeDef          *hdmatx;              /* SPI Tx DMA Handle 
                                                        parameters       */
    DMA_HandleTypeDef          *hdmarx;              /* SPI Rx DMA Handle 
                                                        parameters       */
    HAL_LockTypeDef            Lock;                 /* Locking object      */
    __IO HAL_SPI_StateTypeDef  State;                /* SPI communication state 
                                                      */
    __IO uint32_t              ErrorCode;            /* SPI Error code    */
} SPI_HandleTypeDef;

The SPI_InitTypeDef data structure used in SPI_HandleTypeDef has the following definition:

...

Command	Description	Comments
`spi_flash_test <bus>`	Read the SPI flash device ID	`bus` is the SPI bus number SPI Flash resides on

3. Validating SPI Master Operation

Use the following step-wise procedure to validate the SPI Master mode operation:

Connect a m25p32 SPI Flash device (or a simular similar Flash device) to the SPI1 pins on the carrier board:
- On the STM32H7-BSB Rev 1A board: P2.15 (MISO/PG9), P2.16 (MOSI/PD7), P2.13 (nSS/PG10), P2.12 (SCK/PG11).;
- On the STM32H7-BSB Rev 2A board: P2.3 (MISO/PG9), P2.4 (MOSI/PD7), P2.5 (nSS/PG10), P4.3 (SCK/PA5).

From the FreeRTOS CLI, run the SPI test:

Code Block
CLI> spi_flash_test 1 Manufacturer ID:0x20 Device ID:0x2016 CFD Length:0x10

Compare the output of the spi_flash_test command with the result of the 0x9F command taken from the datasheet for the m25p32 SPI Flash device and listed in the table below:

Manufacturer Identification	Device Identification	CFD Length
0x20	0x2016	0x10

Versions Compared

Old Version 2

New Version Current

Key

1. Understanding SPI Master Mode Interfaces

1.1. FreeRTOS SPI Master Mode Implementation

1.2. FreeRTOS SPI Master Mode C-Binding API

3. Validating SPI Master Operation

Page Comparison

Versions Compared

Old Version 2

New Version Current

Key

1. Understanding SPI Master Mode Interfaces

1.1. FreeRTOS SPI Master Mode Implementation

1.2. FreeRTOS SPI Master Mode C-Binding API

3. Validating SPI Master Operation