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This application note explains how to use the STM32H7 SPI Master mode in the FreeRTOS demo application.
1. Understanding SPI Master Mode Interfaces
1.1. FreeRTOS SPI Master Mode Implementation
The FreeRTOS BSP provides a device driver for the SPI Master mode operation. The driver is configured (enabled / disabled) at the BSP build time, using the HAL_SPI_MODULE_ENABLED configuration option, defined in the stm32h7xx_hal_conf.h file.
1.2. FreeRTOS SPI Master Mode C-Binding API
The SPI Master Mode driver implements the following C-binding API:
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typedef struct { uint32_t Mode; /* Specifies the SPI operating mode. */ uint32_t Direction; /* Specifies the SPI bidirectional mode state. */ uint32_t DataSize; /* Specifies the SPI data size. */ uint32_t CLKPolarity; /* Specifies the serial clock steady state. */ uint32_t CLKPhase; /* Specifies the clock active edge for the bit capture. */ uint32_t NSS; /* Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. */ uint32_t BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which used to configure the transmit and receive SCK clock. */ uint32_t FirstBit; /* Specifies whether data transfers start from MSB or LSB bit. */ uint32_t TIMode; /* Specifies if the TI mode is enabled or not. */ uint32_t CRCCalculation; /* Specifies if the CRC calculation is enabled or not. */ uint32_t CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */ uint32_t CRCLength; /* Specifies the CRC Length used for the CRC calculation. */ uint32_t NSSPMode; /* Specifies whether the NSSP signal is enabled or not. */ uint32_t NSSPolarity; /* Specifies which level of SS input/ output external signal (present on SS pin) is considered as active one. */ uint32_t FifoThreshold; /* Specifies the FIFO threshold level.*/ uint32_t TxCRCInitializationPattern; /* Specifies the transmitter CRC initialization Pattern used for the CRC calculation.*/ uint32_t RxCRCInitializationPattern; /* Specifies the receiver CRC initialization Pattern used for the CRC calculation. */ uint32_t MasterSSIdleness; /* Specifies an extra delay, expressed in number of SPI clock cycle periods, inserted additionally between active edge of SS and first data transaction start in master mode. */ uint32_t MasterInterDataIdleness; /* Specifies minimum time delay (expressed in SPI clock cycles periods) inserted between two consecutive data frames in master mode. */ uint32_t MasterReceiverAutoSusp; /* Control continuous SPI transfer in master receiver mode and automatic management in order to avoid overrun condition. */ uint32_t MasterKeepIOState; /* Control of Alternate function GPIOs state. */ uint32_t IOSwap; /* Invert MISO/MOSI alternate functions. */ } SPI_InitTypeDef; |
2. SPI Master Mode CLI Command
The FreeRTOS application implements the following SPI Master mode related CLI command:
Command | Description | Comments |
spi_flash_test <bus> | Read the SPI flash device ID | bus is the SPI bus number SPI Flash resides on |
3. Validating SPI Master Operation
Use the following step-wise procedure to validate the SPI Master mode operation:
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