Hardware Design Verification Checklist of SOM-NRF9151 Rev 2
1. Overview
This document provides a checklist template for verification of the hardware design.
2. Detailed Verification Results
The following table provides details and up-to-date status on the Hardware Design Verification:
Number | Check Items | Remarks | Done | Comments |
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1 | Double-check design for UART, SPI connections (avoid possible “criss-cross” issues |
| @Vadim Aleynikov (Unlicensed)PASSED |
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2 | Verify that all the signals and interfaces, which presented in the design Block Diagram and/or the list of requirements, were implemented in the design schematics |
| @Vadim Aleynikov (Unlicensed)PASSED |
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3 | Verify that schematics provides the right header (or footer) with board’s name, revision, etc (use Emcraft’s LLC standard header) |
| @Vadim Aleynikov (Unlicensed)PASSED |
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4 | Check that part footprints match their packages |
| @Vadim Aleynikov (Unlicensed)PASSED | Weren’t changed from Rev.1 |
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5 | Align BOM with Emcraft LLC’s BOM (emcraftoperations.xlsx - LIBRARY.xlsx) |
| @Vadim Aleynikov (Unlicensed)PASSED | Kent approved the new parts, but these parts don’t have Emcraft part ## yet. |
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6 | Review BOM with Kent |
| @Vadim Aleynikov (Unlicensed)PASSED | Kent approved the new parts |
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7 | Final review prior to layout (can be a self-review) | Self-review | @Vadim Aleynikov (Unlicensed)PASSED |
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8 | Verify that all relevant hardware debug interfaces available at least on test points. (When in doubt as to requirements, discuss with software teams). |
| @Vadim Aleynikov (Unlicensed)PASSED |
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9 | Verify that all relevant serial console interfaces available at least on test points. (When in doubt as to requirements, discuss with software teams). |
| @Vadim Aleynikov (Unlicensed)PASSED |
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10 | Check that signal vias are tented, but thermal vias aren't tented |
| @Vadim Aleynikov (Unlicensed)PASSED |
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11 | Check that thermal vias differ in size from signal vias and manufacturing notes refer to this size in fabrication instructions |
| @Vadim Aleynikov (Unlicensed)PASSED |
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12 | Check that all the space which isn't used for signal/power is filled with Ground polygons |
| @Vadim Aleynikov (Unlicensed)PASSED |
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13 | Verify that Altium Designer DRC doesn't report errors |
| @Vadim Aleynikov (Unlicensed)PASSED |
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14 | Confirm with Kent that stack-up and via technologies are acceptable |
| @Vadim Aleynikov (Unlicensed)PASSED | The stackup wasn’t changed from Rev.1 |
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15 | Verify that the PCB includes the right markings for key IC’s and interfaces |
| @Vadim Aleynikov (Unlicensed)PASSED |
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16 | Verify that the PCB includes the board name and revision |
| @Vadim Aleynikov (Unlicensed)PASSED |
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17 | Review all views of the silkscreen |
| @Vladimir Khusainov PASSED |
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18 | Final review prior to manufacture (can be a self-review) | Self-review | @Vadim Aleynikov (Unlicensed)PASSED |
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19 | Verify that the PCB project contains the board outline on a separate layer and the Manufacturing file package contains the Board outline gerber and PDF files if the PWB manufacturer needs them. |
| @Vadim Aleynikov (Unlicensed)PASSED |
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